The traditional A algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function\nand sort the OPEN list. To achieve real-time path-planning performance, a hardware acceleratorâ??s architecture called A accelerator\nhas been designed and implemented in field programmable gate array (FPGA). The specially designed 8-port cache and\nOPEN list array are introduced to tackle the calculation bottleneck. The system-on-a-chip (SOC) design is implemented in Xilinx\nKintex-7 FPGA to evaluate A accelerator. Experiments show that the hardware accelerator achieves 37â??75 times performance\nenhancement relative to software implementation. It is suitable for real-time path-planning applications.
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